The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2010
Filed:
Feb. 09, 2007
Applicants:
Peter Ngee Ching Lim, Singapore, SG;
Cheng Huat Tan, Singapore, SG;
Kin Soon Liew, Singapore, SG;
Inventors:
Assignee:
Avago Technologies General IP (Singapore) Pte. Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/26 (2006.01);
U.S. Cl.
CPC ...
Abstract
A system and method for generating a delayed clock signal of an input clock signal involves selectively delaying the input clock signal to produce the delayed clock signal based on the duty cycle of the input clock signal and the duty cycle of a logic signal derived from a logic operation of the input clock signal and the delayed clock signal.
Lim, Peter Ngee Ching. (2010). System and method for generating a delayed clock signal of an input clock signal (U.S. Patent No. 7675339). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7675339
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