The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2010
Filed:
Feb. 16, 2007
Jay T. Young, Louisville, CO (US);
Jay T. Young, Louisville, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method and apparatus for generating an area constraint for a module in a programmable logic device (PLD) is described. In an example, first logic resources are selected in a floorplan of the PLD for implementing a first module of a circuit design. A routing resource area constraint is defined that reserves first routing resources associated with the first logic resources and second routing resources associated with second logic resources. The second routing resources are required for use of the first logic resources. A logic resource area constraint is defined that reserves the first logic resources and excludes the second logic resources. The logic resource constraint area for the module may be non-rectangular or include multiple disjoint regions.