Method using non-linear compression to generate a set of test vectors for use in scan testing an integrated circuit

Abstract

A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector wherein at least two of the coding schemes selected for encoding are different from one another, and wherein one of the available coding schemes represents non-encoded data. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector. Each data block is routed to a plurality of decoders, wherein each decoder is adapted to recognize only one of the coding schemes represented by one of the bit patterns. The decoder recognizing the coding scheme of the data block decodes the bit pattern of the data block and generates the test vectors corresponding to the data block.