The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2010
Filed:
Dec. 27, 2006
Chang Won Park, Kyunggi-do, KR;
Ki Man Jeon, Kyunggi-do, KR;
Young Hwan Kim, Kyunggi-do, KR;
Jae Gi Son, Kyunggi-do, KR;
Hyun Bean Yi, Kyunggi-do, KR;
Sung Ju Park, Kyunggi-do, KR;
Chang Won Park, Kyunggi-do, KR;
Ki Man Jeon, Kyunggi-do, KR;
Young Hwan Kim, Kyunggi-do, KR;
Jae Gi Son, Kyunggi-do, KR;
Hyun Bean Yi, Kyunggi-do, KR;
Sung Ju Park, Kyunggi-do, KR;
Korea Electronics Technology Institute, Sungnam-si, KR;
Abstract
An interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores in a SoC as well as an interconnect wire on a board based on an IEEE 1149.1, and wherein the interconnect delay fault test using different system clocks or core clocks may be carried out simultaneously in one test cycle corresponding to each system clock or core clock even when multiple system clocks or core clocks exists is disclosed.