The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2010

Filed:

Nov. 10, 2006
Applicants:

Alain Chapuis, Riedikon, CH;

Mikhail Guz, San Mateo, CA (US);

Inventors:

Alain Chapuis, Riedikon, CH;

Mikhail Guz, San Mateo, CA (US);

Assignee:

Power-One, Inc., Camarillo, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/26 (2006.01); F02P 3/02 (2006.01); H02H 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A power control system comprises at least one point-of-load (POL) regulator adapted to provide an output voltage to a corresponding load and a system controller operatively connected to the at least one POL regulator via a data bus and adapted to send a first data message in a first format to the at least one POL regulator via the data bus. A bus translator is interposed along the data bus between the at least one POL regulator and the system controller. The bus translator converts the first data message from the first format to a second format that is compatible with the at least one POL regulator. The bus translator is adapted for bi-directional operation to convert a second data message communicated from the at least one POL regulator in the second format to the first format compatible with the system controller. The first and second data formats may comprise either a digital data format or an analog data format. The bus translator may further include a phase-locked loop circuit adapted to synchronize operation of the bus translator to a detected data rate of the data bus.


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