The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2010
Filed:
Jun. 30, 2004
Applicants:
Sridevan Parameswaran, Kensington, AU;
Jorgen Peddersen, Randwick, AU;
Ashley Partis, Rozelle, AU;
Inventors:
Assignee:
Canon Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04M 1/00 (2006.01); H04L 12/28 (2006.01); H04J 3/16 (2006.01); G06F 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
An architecture for selectively powering a receive module () is disclosed. The architecture comprises the receive module () which is functionally adapted, while power is applied to the receive module () by a power module (), and after a power-up time interval has elapsed, to process a traffic packet. The architecture further comprises the power module () that is adapted to apply power to the receive moduledependent upon arrival of a wake-up packet.
Quick Actions:
Parameswaran, Sridevan. (2010). Low power chip architecture (U.S. Patent No. 7672694). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7672694
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile