High-speed serial transceiver with sub-nominal rate operating mode

Abstract

A communication device comprises a receiver and a data recovery module. The receiver may be an element of a serial transceiver embedded in or otherwise associated with an FPGA or other type of reconfigurable hardware. The receiver is operable with an unlocked sampling clock. The data recovery module is configured to detect transition edges in data signal samples generated by the receiver using the unlocked sampling clock, and to determine from the detected edges a sampling point for use in recovery of the associated data. The data recovery module is further configured to provide adjustment in the sampling point in the presence of transition edge variations, such as one or more exception conditions, that are attributable to the unlocked sampling clock.