Built-in-self test for high-speed serial bit stream multiplexing and demultiplexing chip set

Abstract

A bit stream multiplexer includes an input ordering block, a plurality of multiplexers, an output ordering block, and a Pseudo Random Bit Stream (PRBS) function. The input ordering block is operates to receive a first plurality of transmit bit streams at a first bit rate, order the first plurality of transmit bit streams based upon a first order select signal, and produce a first plurality of ordered transmit bit streams at the first bit rate. The input ordering block may also deskew the first plurality of transmit bit streams. The plurality of multiplexers operate to receive the first plurality of ordered transmit bit streams at the first bit rate and produce an interface plurality of transmit bit streams at an interface bit rate. The output ordering block operates to order the interface plurality of transmit bit streams based upon an interface order select signal. The PRBS function produces a PRBS that is coupled to at least one of the interface plurality of transmit bit streams. A bit stream demultiplexer is similarly constructed.