The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2010
Filed:
Jul. 09, 2008
Corey Kenneth Barrows, Colchester, VT (US);
Douglas W. Kemerer, Essex Junction, VT (US);
Stephen Gerard Shuma, Underhill, VT (US);
Douglas Willard Stout, Milton, VT (US);
Oscar Conrad Strohacker, Leander, TX (US);
Mark Steven Styduhar, Hinesburg, VT (US);
Paul Steven Zuchowski, Jericho, VT (US);
Corey Kenneth Barrows, Colchester, VT (US);
Douglas W. Kemerer, Essex Junction, VT (US);
Stephen Gerard Shuma, Underhill, VT (US);
Douglas Willard Stout, Milton, VT (US);
Oscar Conrad Strohacker, Leander, TX (US);
Mark Steven Styduhar, Hinesburg, VT (US);
Paul Steven Zuchowski, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.