The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2010

Filed:

Sep. 14, 2006
Applicants:

Victor Martinus Gerardus Van Acht, Waalre, NL;

Nicolaas Lambert, Waalre, NL;

Andrei Mijiritskii, Zaltbommel, NL;

Pierre Hermanus Woerlee, Valkenswaard, NL;

Inventors:

Victor Martinus Gerardus Van Acht, Waalre, NL;

Nicolaas Lambert, Waalre, NL;

Andrei Mijiritskii, Zaltbommel, NL;

Pierre Hermanus Woerlee, Valkenswaard, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

A logic assembly () is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry () having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current paths being coupled to a common node that forms an output of logic assembly (). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit () for boosting the output of said logic assembly () including a capacitive means () for enabling supply of additional charge to the output of said logic assembly (). It further includes a bootstrapping circuit () for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.


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