Superscale processor performance enhancement through reliable dynamic clock frequency tuning

Abstract

In the case of a pipelined processor, a performance gain is achievable through dynamically generating a main clock signal associated with a synchronous logic circuit and generating at least one backup register clock signal, the backup register clock signal at the same frequency as the main clock signal and phase shifted from the main clock signal to thereby provide additional time for one or more of the logic stages to execute. Error detection or error recovery may be performed using the backup registers. The methodology can further be extended, to design a system with cheaper technology and simple design tools that initially operates at slower speed, and then dynamically overclocks itself to achieve improved performance, while guaranteeing reliable execution.