The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2010

Filed:

May. 30, 2006
Applicants:

Weidong Tian, Dallas, TX (US);

Bradley Sucher, McKinney, TX (US);

Zafar Imam, Dallas, TX (US);

Inventors:

Weidong Tian, Dallas, TX (US);

Bradley Sucher, McKinney, TX (US);

Zafar Imam, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/60 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (), obviating overstress or break down damage to a focal device structure () that might result from uncontrolled dissipation of the aberrant charge. A substrate () has first and second intermediate structures () disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure () is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure () is disposed contiguously atop the first conductive structure and the first intermediate layer. A void () is formed in a peripheral region () of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure () is disposed atop the third intermediate structure such that it couples the substrate through the void.


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