The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2010

Filed:

Mar. 26, 2007
Applicants:

Balaji Ganesan, Fairview, OR (US);

David Vinke, Happy Valley, OR (US);

Ekambaram Balaji, Portland, OR (US);

Nicholas A. Oleksinski, Northville, MI (US);

Inventors:

Balaji Ganesan, Fairview, OR (US);

David Vinke, Happy Valley, OR (US);

Ekambaram Balaji, Portland, OR (US);

Nicholas A. Oleksinski, Northville, MI (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.


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