Timing analysis method, timing analysis program, and timing analysis tool

Abstract

This invention intends to provide timing analysis methods, timing analysis programs, and timing analysis tools for the purpose of performing timing verification in optimum conditions without any excessive variations by statistically dealing with variations in elemental devices forming a semiconductor integrated circuit. In order to verify a timing between two signals, a delay value of a signal propagating through a signal path selected as a candidate for timing analysis is obtained, and with respect to a random variation amount of the delay value, a random variation amount corresponding to the number of gate circuit stages forming the signal path is obtained. Then, based on the delay value and the random variation amount, a most severe variation amount between the two signals in a most severe operating condition is obtained, and based on the most severe variation amount, a respective individual variation coefficient is allocated for each gate circuit, thereby performing a timing analysis.