The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2010
Filed:
Mar. 07, 2007
Peter Boyle, Mountain View, CA (US);
Iliya G. Zamek, San Jose, CA (US);
Zhe LI, Sunnyvale, CA (US);
Lawrence David Smith, San Jose, CA (US);
Peter Boyle, Mountain View, CA (US);
Iliya G. Zamek, San Jose, CA (US);
Zhe Li, Sunnyvale, CA (US);
Lawrence David Smith, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Computer-aided design tools analyze a custom logic design for a programmable logic device integrated circuit. The tools identify distinct clock domains in the design. The tools also identify which of the clock domains are synchronous. The tools examine the synchronous clock domains to determine which of the clock domains have required fixed phase relationships. Clocks for clock domains that do not have required fixed relationships can be adjusted in phase to minimize power supply simultaneous switching noise. Noise may be minimized by making clock phase adjustments using a programmable phase-locked loop circuit.