Hardware-efficient low density parity check code for digital communications

Abstract

A low density parity check (LDPC) code for a belief propagation decoder circuit is disclosed. LDPC code is arranged as a macro matrix (H) representing block columns and block rows of a corresponding parity check matrix (H). Each non-zero entry corresponds to a permutation matrix with a shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns are grouped, so that only one column in the group contributes to the parity check sum in a row. A parity check value estimate memory is arranged in banks logically connected in various data widths and depths. A parallel adder generates extrinsic estimates for generating new parity check value estimates that are forwarded to bit update circuits for updating of probability values. Parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.