The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2010
Filed:
Sep. 01, 2006
Wayne E. Wennekamp, Rio Rancho, NM (US);
Randal Kuramoto, San Carlos, CA (US);
James A. Walstrum, Jr., San Jose, CA (US);
Sanja Srivastava, San Jose, CA (US);
Neil G. Jacobson, Los Altos, CA (US);
Wayne E. Wennekamp, Rio Rancho, NM (US);
Randal Kuramoto, San Carlos, CA (US);
James A. Walstrum, Jr., San Jose, CA (US);
Sanja Srivastava, San Jose, CA (US);
Neil G. Jacobson, Los Altos, CA (US);
XILINX, Inc., San Jose, CA (US);
Abstract
A memory coupled to a programmable logic device (PLD) is configured through the PLD's JTAG port. A soft core loaded into the PLD connects to the JTAG port and memory. An external programming host device connects to the JTAG port, sends instructions and data to and receives data from the memory via the JTAG port and soft core. A synchronization JTAG instruction is loaded, and a Shift Data state of the JTAG port state machine is used. The programming host device and soft core are synchronized, and a memory chip select is asserted. A memory instruction, such as READ, WRITE or ERASE is loaded into the memory. An RTI state of the state machine is used to wait for instruction completion and the chip select is deasserted. Another instruction is processed starting with using the Shift Data state. Alternatively, a PLD Shift Data Register is used in conjunction with the soft core.