The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2010

Filed:

Sep. 27, 2006
Applicants:

Hemang Maheshkumar Parekh, San Jose, CA (US);

Hai-jo Tarn, San Jose, CA (US);

Gabor Szedo, San Jose, CA (US);

Vanessa Yu-mei Chou, San Jose, CA (US);

Jeffrey Allan Graham, Sydney, AU;

Elizabeth R. Cowie, Edinburgh, GB;

Inventors:

Hemang Maheshkumar Parekh, San Jose, CA (US);

Hai-Jo Tarn, San Jose, CA (US);

Gabor Szedo, San Jose, CA (US);

Vanessa Yu-Mei Chou, San Jose, CA (US);

Jeffrey Allan Graham, Sydney, AU;

Elizabeth R. Cowie, Edinburgh, GB;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of buffering data in a circuit processing data in both a natural address order and a modified address order is described. The method comprises the steps of storing a first block of data according to a first addressing order of a natural address order or a modified address order; reading the first block of data stored in a buffer according to the other addressing order of the natural address order and the modified address order; and simultaneously writing a second block of data to the buffer in the other addressing order while reading the first block of data stored in a buffer according to the other addressing order.


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