The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2010

Filed:

Sep. 02, 2005
Applicant:

Daniele Lo Iacono, Reggio Calabria, IT;

Inventor:

Daniele Lo Iacono, Reggio Calabria, IT;

Assignee:

STMicroelectronics S.R.L., Agrate Brianza (MI), IT;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04W 88/02 (2009.01);
U.S. Cl.
CPC ...
Abstract

A data processor unit includes at least two operation-execution units, each one adapted to receive input data, perform a respective operation on the input data and outputting output data resulting after applying said operation; the data processor unit further includes: a data storage unit including at least two individually-accessible memory devices adapted to store data; a programmable controller adapted to be programmed so as to execute a selected program; a first data routing circuit arrangement adapted to receive data from the at least two memory devices, from the programmable controller and from a second data routing circuit arrangement, and for selectively routing selected ones among the received data to the input of the operation-execution units; the second data routing circuit arrangement is adapted to receive the output data outputted by the operation-execution units and to selectively route the output data to the at least two memory devices, to the programmable controller, and to the first data routing circuit arrangement. The programmable controller is operatively coupled to the at least two operation-execution units, to the first and second data routing circuit arrangements, and to the at least two memory devices for controlling the operation thereof.


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