The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2010
Filed:
Jan. 18, 2006
Takahisa Hatano, Hokkaido, JP;
Kosho Suzuki, Hokkaido, JP;
Takahisa Hatano, Hokkaido, JP;
Kosho Suzuki, Hokkaido, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A PWM generation circuit is set so as to generate a PWM pulse signal having a frequency that is an odd number times a vertical synchronization frequency. A frequency division circuit frequency-divides the PWM pulse signal generated by the PWM generation circuit. An AND gate calculates the logical product of the PWM pulse signal generated by the PWM generation circuit and a frequency-division pulse signal outputted from the frequency division circuit. An OR gate calculates the logical sum of the PWM pulse signal generated by the PWM generation circuit and the frequency-division pulse signal outputted from the frequency division circuit. A selector outputs an output signal of the OR gate as a dimming pulse signal in a case where the set duty ratio is not less than 50%, while outputting an output signal of the AND gate as a dimming pulse signal in a case where the set duty ratio is less than 50%. Consequently, the frequency of the dimming pulse signal is five-second the frequency of a vertical synchronizing signal.