The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2010
Filed:
Jul. 25, 2008
Ying-fang Xu, Jiang-Su, CN;
Ning-hua LI, Jiang-Su, CN;
Chin-mei Huang, Taichung, TW;
Tsui-chuan Wang, Dali, TW;
Ying-Fang Xu, Jiang-Su, CN;
Ning-Hua Li, Jiang-Su, CN;
Chin-Mei Huang, Taichung, TW;
Tsui-Chuan Wang, Dali, TW;
Wintek Corporation, Taichung, TW;
Abstract
The present invention discloses a flexible printed circuit (FPC) layout and a method thereof. The flexible printed circuit (FPC) layout method comprises steps of: providing a circuit board body; disposing at least an electroplating point on the circuit board body; disposing a plurality of solder pads on the circuit board body, the plurality of solder pads comprising at least a first solder pad and at least a second solder pad being connected respectively to the electroplating point through an internal wire, the first solder pad being further connected to an electroplating zone on the circuit board body through an external wire; performing an electroplating process from the electroplating zone through the external wire so that the external wire, the first solder pad connected to the external wire, the electroplating point connected through the internal wire to the first solder pad, and the second solder pad connected through the internal wire to the electroplating point are electroplated and electrically connected; and providing at least a via hole at the electroplating point on the circuit board body to form an open circuit between the first solder pad and the second solder pad. By using the disclosed method, the flexible printed circuit layout of the present invention can be formed.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile