The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2010
Filed:
Sep. 15, 2008
Bruce B. Doris, Brewster, NY (US);
Young-hee Kim, Yorktown Heights, NY (US);
Barry P. Linder, Hastings-on-Hudson, NY (US);
Vijay Narayanan, New York, NY (US);
Vamsi K. Paruchuri, New York, NY (US);
Bruce B. Doris, Brewster, NY (US);
Young-Hee Kim, Yorktown Heights, NY (US);
Barry P. Linder, Hastings-on-Hudson, NY (US);
Vijay Narayanan, New York, NY (US);
Vamsi K. Paruchuri, New York, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of fabricating a complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a method of fabricating a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile