The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2010
Filed:
Jun. 10, 2005
Koji Nakamuta, Kawasaki, JP;
Yoshito Koyama, Kawasaki, JP;
Koji Nakamuta, Kawasaki, JP;
Yoshito Koyama, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A DPLL circuit is provided for making it possible to inhibit an initial frequency offset during holdover. The DPLL circuit includes a slave oscillator for generating a frequency signal corresponding to the size of a control signal value; a phase difference detection circuit for detecting the difference in phase between the output of said slave oscillator and the inputted reference clock, and outputting a digital signal of the prescribed number of bits corresponding to said detected phase difference; and a holdover unit for generating a correction value based on the output of said phase difference detection circuit, wherein when the holdover is detected, said holdover unit periodically adds the correction value to the output of said phase difference detection circuit to obtain a control value for said slave oscillator.