The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2010
Filed:
Jun. 27, 2008
Farookh Moogat, Fremont, CA (US);
Raul-adrian Cernea, Santa Clara, CA (US);
Shou-chang Tsao, San Jose, CA (US);
Tai-yuan Tseng, Milpitas, CA (US);
Farookh Moogat, Fremont, CA (US);
Raul-Adrian Cernea, Santa Clara, CA (US);
Shou-Chang Tsao, San Jose, CA (US);
Tai-Yuan Tseng, Milpitas, CA (US);
Sandisk Corporation, Milpitas, CA (US);
Abstract
A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.