Dynamic random access memory (dram) for suppressing a short-circuit current

Abstract

A semiconductor memory device which has a normal memory cell array and a redundant memory cell array for replacing a failure bit in the normal memory cell array, having: a memory cell array having a plurality of word lines, a plurality of bit line pairs crossing the word lines, and a plurality of memory cells placed at the crossing positions; and a plurality of sense amplifier circuits which are placed between adjacent memory cell arrays and are shared by bit line pairs of memory cell arrays on both sides. And a current interrupting circuit for disconnecting the sense amplifier and the bit line pairs in a column having a failure is formed respectively between the sense amplifier circuit and the bit line pairs on both sides. By this current interrupting circuit, short-circuit current from the sense amplifier circuit to the shorted area can be suppressed.