The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2010
Filed:
Feb. 20, 2008
Simon Tam, Cambridgeshire, GB;
Simon Tam, Cambridgeshire, GB;
Seiko Epson Corporation, Tokyo, JP;
Abstract
An organic TFT (OTFT) inverter arrangement comprises an inverter stage including a series arrangement of first and second MOS OTFTs (T, T) connected between first and second supply terminals (VDD), the first and second OTFTs having first and second gates, respectively. An input terminal (V) is connected to the first gate, while an output terminal (V) is connected to the node interconnecting the first and second OTFTs (T, T). A bias-control stage is connected between the first gate and the second gate. The bias-control stage is an inverting stage, such that, when an input voltage on the first gate rises, a voltage on the second gate falls, and vice-versa. The bias-control stage comprises a series arrangement of third and fourth OTFTs (T, T) connected between the first and second supply terminals (V, V), and a series arrangement of fifth and sixth OTFTs (T, T) connected between the first and second supply terminals (V, V). The fifth and sixth OTFTs (T, T) are controlled by the third and fourth OTFTs (T, T) and feed the first and second gates, respectively. The OTFT inverter arrangement may be used as the basis of an OTFT logic-gate arrangement.