The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2010
Filed:
Dec. 29, 2006
Hirotaka Kawata, Suwa, JP;
Hirotaka Kawata, Suwa, JP;
Seiko Epson Corporation, Tokyo, JP;
Abstract
A substrate for an electro-optical device includes a plurality of scanning lines arranged in rows; a plurality of data lines arranged in columns and grouped into blocks, each of the blocks including n data lines, where n indicates an integer of 2 or more; a plurality of terminals that receive data signals for the corresponding blocks; a demultiplexer that selects a data line designated by a control signal from among the n data lines within each of the blocks and that supplies to the data line selected in the block the corresponding data signal received by the corresponding terminal for the block; a plurality of pixels disposed in association with intersections of the plurality of scanning lines and the plurality of data lines, some or all of the plurality of pixels performing display in accordance with the data signals supplied to the data lines when selection of the corresponding scanning lines is performed; and a checking circuit. The checking circuit includes n read lines; a plurality of first switches each provided for a different data line, one end of each of the plurality of first switches being connected to a corresponding data line and the other end of each of the plurality of first switches being connected to one of the n read lines such that the other ends of the plurality of first switches corresponding to the n data lines belonging to an identical block are connected to different read lines; and a shift register that selects one of the blocks so as to allow conduction of first switches whose other ends are connected to the n data lines belonging to the selected block.