The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2010

Filed:

Jun. 19, 2006
Applicants:

Oliver Nehrig, Kirchdorf, DE;

Rudiger Ganz, Freising, DE;

Inventors:

Oliver Nehrig, Kirchdorf, DE;

Rudiger Ganz, Freising, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 27/26 (2006.01); H03K 5/01 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of capacitance-to-voltage conversion with an external sensor capacitor (C) and a capacitance-to-voltage converter () implemented on an integrated readout circuit that includes a reference capacitor (C), a sampling capacitor (C) and a sampling amplifier () and which has input terminals () to which the sensor capacitor (C) is connected. The method comprises the steps of a) applying a reference voltage (V) to the series connected sensor capacitor (C) and reference capacitor (C) and charging the sampling capacitor (C) to the potential at the interconnection node (A) between the sensor capacitor (C) and the reference capacitor (C), b) connecting the sampling capacitor (C) to inputs of the sampling amplifier. The method further comprises the steps of c) applying the reference voltage (V) to the series connected sensor capacitor (C) and reference capacitor (C) with a polarity opposite to that in step a) and charging the sampling capacitor (C) to the potential at the interconnection node (A) between the sensor capacitor (C) and the reference capacitor (C) and d) connecting the sampling capacitor (C) to the inputs of the sampling amplifier in a polarity opposite to that in step b).


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