The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2010

Filed:

Jul. 24, 2007
Applicants:

Patty Pei-ling Chang-chien, Redondo Beach, CA (US);

Kelly Jill Tornquist Hennig, Torrance, CA (US);

Ken Wai-kin Ho, Alhambra, CA (US);

Ann Kent-ming Ho, Temple City, CA (US);

Inventors:

Patty Pei-Ling Chang-Chien, Redondo Beach, CA (US);

Kelly Jill Tornquist Hennig, Torrance, CA (US);

Ken Wai-Kin Ho, Alhambra, CA (US);

Ann Kent-Ming Ho, Temple City, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating wafer-level packages including lateral interconnects. The method includes precutting a cover wafer at the locations where the cover wafer will be completely cut through to separate the wafer-level packages. The cover wafer is bonded to the substrate wafer using bonding rings so as to seal the integrated circuit within a cavity between the cover wafer and the substrate wafer, where the precuts face the substrate wafer. The cover wafer is then cut at the precut locations to remove the unwanted portions of the cover wafer between the packages and expose contacts or probe pads for the lateral interconnects. The substrate wafer is then cut between the wafer-level packages to separate the packages.


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