The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2010

Filed:

Mar. 03, 2004
Applicant:

Yasuhiro Wakisaka, Tokyo, JP;

Inventor:

Yasuhiro Wakisaka, Tokyo, JP;

Assignee:

Zeon Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

A process for producing a multilayer printed wiring board, comprising providing an uncured or partly-cured resin layer from a curable composition comprising an insulation polymer and a curable agent, the resin layer superimposed on an internal layer substrate having a first conductive layer as an outermost layer; bringing the surface of the resin layer into contact with a compound having a structure capable of coordination with a metal; curable the resin layer to thereby form an electrical insulation layer; oxidizing the surface of the obtained electrical insulation layer until the surface average roughness (Ra) of the electrical insulation layer falls within the range of 0.05 to less than 0.2 μm and the surface ten-point average roughness (Rzjis) thereof within the range of 0.3 to less than 4 μm; and forming a second conductive layer on the electrical insulation layer by plating operation. There is further provided a multilayer printed wiring board produced by the process. This multilayer printed wiring board excels in pattern adhesion to substrates, even those of large size.


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