Memory and i/o bridge

Abstract

The present invention is directed to an improved memory and I/O bridge that provides an improved interface for communicating data between the data bus of the system processor and the memory controller. The memory and I/O bus bridge according to the present invention provides increased performance in the system. The memory and I/O bridge can include a deep memory access request FIFO to queue up memory access requests when the memory controller is busy. The memory and I/O bridge can include a memory write data buffer for holding and merging memory write operations to the same page of memory. The memory and I/O bridge can include a memory read data buffer for holding and queuing data and instructions read from memory, waiting to be forward to the data bus. The memory data read buffer can operate in one or more software selectable prefetch modes, which can cause one or more pages to be read in response to a single memory read instruction. The memory read data buffer can satisfy memory read request for data or instructions already held in the memory read buffer without reading the data or instructions from memory. The memory read data buffer can also provide for data coherency with respect the memory write data buffer and the external memory. The memory and I/O bridge can also include performance counters for tracking information about the performance of the memory and I/O bridge in order to tune the software operation and determine the optimum prefetch mode for a given application.