Abitration circuit providing stable operation regardless of timing for read and write requests

Abstract

The present invention provides an arbitration circuit capable of stable operation regardless of timings for read and write requests. A latch signal of a predetermined pulse width is generated in accordance with a read request signal or a write request signal and supplied to latches. Flip-flops or FFs respectively fetch therein write and read requests produced within the time of the latch signal. The latches respectively output the fetched requests as signals at the same timing. Thus, since the timings for the signals coincide with each other even when the write request and the read request are made at close intervals while the latch signal is being outputted from a latch controller, a write control signal or a read control signal can be stably outputted in accordance with the order of priority defined in advance by a delay unit.