The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2010

Filed:

Mar. 13, 2007
Applicants:

Eric D. Schneider, Shorewood, MN (US);

Gary Nachazel, Dayton, MN (US);

John Ryan, Maple Grove, MN (US);

Inventors:

Eric D. Schneider, Shorewood, MN (US);

Gary Nachazel, Dayton, MN (US);

John Ryan, Maple Grove, MN (US);

Assignee:

Eridon Corporation, Shorewood, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/00 (2006.01); H01L 25/00 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods for configuring an embedded system are described. One method includes connecting a plurality of add-on cards to a circuit board having a programmable processor. The programmable processor is configured to communicate with the plurality of add-on cards. At least one add-on card connects to a circuit board utilizing two or more connectors. The method also includes determining an identifier of each of the plurality of add-on cards, where the identifier of each of the plurality of add-on cards is used to generate a configuration image. Further included is configuring the programmable processor to communicate with the plurality of add-on cards by obtaining the configuration image. In some examples, the programmable processor is an FPGA.


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