The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2010
Filed:
Feb. 20, 2004
Leon Zheng, San Jose, CA (US);
Martin Langhammer, Southway Alderbury, GB;
Nitin Prasad, Milpitas, CA (US);
Greg Starr, San Jose, CA (US);
Chiao Kai Hwang, Fremont, CA (US);
Kumara Tharmalingam, Santa Clara, CA (US);
Leon Zheng, San Jose, CA (US);
Martin Langhammer, Southway Alderbury, GB;
Nitin Prasad, Milpitas, CA (US);
Greg Starr, San Jose, CA (US);
Chiao Kai Hwang, Fremont, CA (US);
Kumara Tharmalingam, Santa Clara, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.