The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2010

Filed:

Jun. 28, 2004
Applicants:

Stephen E. Strickland, Marlborough, MA (US);

John V. Burroughs, Mason, NH (US);

Bassem N. Bishay, Attleboro, MA (US);

Steven D. Sardella, Marlborough, MA (US);

Inventors:

Stephen E. Strickland, Marlborough, MA (US);

John V. Burroughs, Mason, NH (US);

Bassem N. Bishay, Attleboro, MA (US);

Steven D. Sardella, Marlborough, MA (US);

Assignee:

EMC Corporation, Hopkinton, MA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04J 3/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A data storage system includes a first storage processor for storing and retrieving data from a data storage array for at least one host computer; a second storage processor, coupled to the first storage processor by a communication link, for storing and retrieving data from the data storage array for the at least one host computer; a number M of multiplexers, M being greater than one, each of the multiplexers being coupled to the first storage processor and the second storage processor for receiving data signals from the first storage processor and the second storage processor and transmitting the data signals to a disk drive device; a number A of arbiters, each being coupled to the first storage processor, the second storage processor and a number N of the plurality of multiplexers, for receiving arbiter control signals from the first storage processor and the second storage processor and transmitting multiplexer control signals to each of the number N of the plurality of multiplexers; and a midplane device coupled between the plurality of multiplexers and the data storage array for transferring the data signals from the plurality of multiplexers to the data storage array. The first storage processor, the second storage processor, the plurality of multiplexers, the plurality of arbiters and the midplane are all mounted on a single printed circuit board.


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