The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2010
Filed:
Aug. 11, 2008
Joseph O. Marsh, Poughkeepsie, NY (US);
Jeremy Stephens, Seattle, WA (US);
Charlie C. Hwang, Wappingers Falls, NY (US);
James S. Mason, Eastleigh, GB;
Huihao Xu, Brooklyn, NY (US);
Matthew B. Baecher, Newburgh, NY (US);
Thomas J. Bardsley, Poughkeepsie, NY (US);
Mark R. Taylor, Essex Junction, VT (US);
Joseph O. Marsh, Poughkeepsie, NY (US);
Jeremy Stephens, Seattle, WA (US);
Charlie C. Hwang, Wappingers Falls, NY (US);
James S. Mason, Eastleigh, GB;
Huihao Xu, Brooklyn, NY (US);
Matthew B. Baecher, Newburgh, NY (US);
Thomas J. Bardsley, Poughkeepsie, NY (US);
Mark R. Taylor, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal. The testing includes skewing a differential output termination impedance, adjusting a differential receiver circuit voltage offset, selecting a differential driver circuit power level, enabling a decoder which activates only one differential driver circuit segment per test sequence, activating a segment, stimulating the differential driver circuit with digital test patterns, receiving differential driver circuit output, converting the output to a single-ended signal, and observing the single-ended signal.