The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2010
Filed:
Nov. 30, 2006
Youang Pin Chen, Allentown, PA (US);
Sireesha Tulluri Lakshmi Naga Venkata Srujana, Bangalore, IN;
Nirav Patel, Bangalore, IN;
Raghunatha Reddy Lakki Reddy, Bangalore, IN;
Sivaramakrishnan Subramanian, Bangalore, IN;
Venkat Rao Vallapaneni, Bangalore, IN;
Youang Pin Chen, Allentown, PA (US);
Sireesha Tulluri Lakshmi Naga Venkata Srujana, Bangalore, IN;
Nirav Patel, Bangalore, IN;
Raghunatha Reddy Lakki Reddy, Bangalore, IN;
Sivaramakrishnan Subramanian, Bangalore, IN;
Venkat Rao Vallapaneni, Bangalore, IN;
Agere Systems Inc., Allentown, PA (US);
Abstract
A processor-implemented means of designing a power pad layout includes determining a location of at least one ESD structure so as to minimize a placement cost and determining a location of at least one connection between the at least one ESD structure and at least one power ring. The step of determining a location of at least one connection between the ESD structure and at least one power ring may include the steps of determining a minimum spanning tree of elements associated with a given power ring; and back-tracing through a minimum spanning tree of elements associated with a given power ring in order to determine a minimal list of routed paths among the elements.