The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2010
Filed:
Apr. 10, 2008
Przemek Guzy, Richmond Hill, CA;
Steven Caranci, Toronto, CA;
Przemek Guzy, Richmond Hill, CA;
Steven Caranci, Toronto, CA;
Altera Corporation, San Jose, CA (US);
Abstract
Methods are provided for presenting delay characteristics of a circuit design. The methods acquire routing delay data and logic delay data for each of a number of paths within the circuit design. In one method, a scatterplot of the routing delay data versus the logic delay data for each of the paths is generated and rendered. In another method, the paths are specified as being associated with modules within the circuit design. In this method, a histogram plot of the paths within each module is generated, wherein the paths within each module are identified as being dominated by routing delay or logic delay. In another embodiment, a connectivity diagram is generated to convey an amount of connectivity within modules and between modules. Each of the methods can be implemented as program instructions on a computer readable medium.