The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2010

Filed:

Jun. 30, 2007
Applicants:

Edwin DE Angel, Austin, TX (US);

Jorge Antonio Abullarade, Austin, TX (US);

Jean Charles Pina, Austin, TX (US);

Rahul Singh, Austin, TX (US);

Inventors:

Edwin De Angel, Austin, TX (US);

Jorge Antonio Abullarade, Austin, TX (US);

Jean Charles Pina, Austin, TX (US);

Rahul Singh, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus for automatically securing non-volatile (NV) storage in an integrated circuit provides improved resistance to code copying and reverse-engineering attacks. External interfaces that provide read access to the NV storage are be disabled, for a predetermined time after a reset or other initialization signal is received. An internal lock state bit or key is checked as well as an external lock prevent indication. If the lock prevent indication is not received, or the internal lock state bit is already set, then the integrated circuit is operated under a locked condition, in which external access to the NV storage values is prevented. The lock prevent indication may be a signal provided during reset of the integrated circuit on a terminal that is used for another purpose after initialization of the integrated circuit.


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