The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2010
Filed:
Mar. 22, 2005
Applicant:
Takashi Oshima, Chiba, JP;
Inventor:
Takashi Oshima, Chiba, JP;
Assignee:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
Plural second logic blocks are set to a first logic block, and when data is written to the second logic block, write waiting is given using an address next to the address of the current second logic block. In order to protect data of the written second logic block, the next address is skipped using another address as an expected value.
Oshima, Takashi. (2010). Method of controlling a semiconductor memory device applied to a memory card (U.S. Patent No. 7657697). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7657697
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