The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2010
Filed:
Dec. 02, 2004
Mack Wayne Riley, Austin, TX (US);
Daniel Lawrence Stasiak, Austin, TX (US);
Michael Fan Wang, Austin, TX (US);
Stephen Douglas Weitzel, Round Rock, TX (US);
Mack Wayne Riley, Austin, TX (US);
Daniel Lawrence Stasiak, Austin, TX (US);
Michael Fan Wang, Austin, TX (US);
Stephen Douglas Weitzel, Round Rock, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.