The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2010
Filed:
Jan. 26, 2005
Bily Wang, Hsin Chu, TW;
Jonnie Chuang, Pan Chiao, TW;
Chuan-fa Lin, Shu Lin, TW;
Chi-wen Hung, Chung Li, TW;
Bily Wang, Hsin Chu, TW;
Jonnie Chuang, Pan Chiao, TW;
Chuan-Fa Lin, Shu Lin, TW;
Chi-Wen Hung, Chung Li, TW;
Harvatek Corporation, Hsin Chu, TW;
Abstract
A wafer-level electro-optical semiconductor fabrication mechanism and method for the same which improves upon traditional electro-optical semiconductor grain packaging methods. The present invention electrically connects semiconductor grains to the grains on a top surface of a wafer, this is done by either screen-printing or steel board-printing solder or silver paste onto the wafer. After that, the wafer is processed using the following steps: processing the devices, bonding with wire, packaging the wafer and finally cutting the wafer. Using this method raises the production yield while production times and costs are reduced. The wafer-level electro-optical semiconductor fabrication mechanism comprises: a wafer, an electro-optical semiconductor grain and conductive materials.