The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2010

Filed:

May. 31, 2007
Applicants:

Shuichi Takahashi, Gunma, JP;

Yutaka Yamada, Gunma, JP;

Masaru Kanai, Gunma, JP;

Inventors:

Shuichi Takahashi, Gunma, JP;

Yutaka Yamada, Gunma, JP;

Masaru Kanai, Gunma, JP;

Assignee:

Sanyo Electric Co., Ltd., Moriguchi-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/119 (2006.01); H01L 21/332 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention is directed to providing a resistor with high reliability. The invention is also directed to miniaturizing a semiconductor device having a MOS transistor and a resistor element on the same semiconductor substrate. An N-type well region is formed in a front surface of a P-type semiconductor substrate, and a P-type resistor layer is formed in a front surface of the well region. A conductive layer is annularly formed on the well region so as to surround the resistor layer. A predetermined voltage is applied to the conductive layer and a channel is not formed under the conductive layer during normal operation, thereby isolating a pull-down resistor from the other elements (e.g. a P-channel type MOS transistor). The resistor layer and an element isolation insulation film do not contact each other. Both the PMOS and the pull-down resistor are formed in one region surrounded by the element isolation insulation film.


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