The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2010

Filed:

Sep. 13, 2004
Applicants:

Takuji Maeda, Neyagawa, JP;

Shinji Inoue, Neyagawa, JP;

Yoshiho Gotoh, Osaka, JP;

Jun Ohara, Imabari, JP;

Masahiro Nakanishi, Yawata, JP;

Shoichi Tsujita, Kyoto, JP;

Tomoaki Izumi, Neyagawa, JP;

Tetsushi Kasahara, Katano, JP;

Kazuaki Tamura, Toyono-gun, JP;

Kiminori Matsuno, Katano, JP;

Koichi Horiuchi, Nara, JP;

Manabu Inoue, Hirakata, JP;

Inventors:

Takuji Maeda, Neyagawa, JP;

Shinji Inoue, Neyagawa, JP;

Yoshiho Gotoh, Osaka, JP;

Jun Ohara, Imabari, JP;

Masahiro Nakanishi, Yawata, JP;

Shoichi Tsujita, Kyoto, JP;

Tomoaki Izumi, Neyagawa, JP;

Tetsushi Kasahara, Katano, JP;

Kazuaki Tamura, Toyono-gun, JP;

Kiminori Matsuno, Katano, JP;

Koichi Horiuchi, Nara, JP;

Manabu Inoue, Hirakata, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A host information memory is provided in a semiconductor memory card and a data write start address and a data size supplied by an access unit are stored. A free physical area generation section determines whether or not to perform erasing of an invalid block of a nonvolatile memory when writing of data based on the data write start address and data size, and determines the number of blocks to be erased. When erasing, writing of data and erasing of invalid blocks are simultaneously performed with respect to different memory chips. Erase process of data, herewith, can be optimized and high speed access from the access unit to a semiconductor memory card can be realized.


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