Memory system with memory controller and board comprising a digital buffer wherein input/output data and clock signals are applied in parallel

Abstract

A digital registered data buffer is disclosed that has data paths each with a data input for receiving a digital data input signal (Dn), a clock input for receiving a clock input signal (CLK) and a data output providing a digital data output signal (Qn) for application to a data destination device such as memory devices. The buffer further has a clock output for providing an output clock signal (QCLK) to the data destination device and a phase-locked loop (PLL) with a clock input, a feedback input, a feedback output and a plurality of clock outputs. The buffer uses a pair of data registers, i.e. flip-flops (FF, FF) connected in series in each data path. The first data register in each data path is clocked by the clock input signal (CLK) and the second data register in each data path is clocked by one of the clock outputs (PDCLK) from the PLL.