The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 2010
Filed:
Mar. 31, 2008
Andrew E. Horch, Seattle, WA (US);
Bin Wang, Seattle, WA (US);
Andrew E. Horch, Seattle, WA (US);
Bin Wang, Seattle, WA (US);
Virage Logic Corporation, Fremont, CA (US);
Abstract
The present disclosure provides a Non-Volatile Memory (NVM) cell and programming method thereof. The cell can denote at least two logic levels. The cell has a read-transistor with a floating gate, and Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased with a first gate bias voltage such that the BTBT device is in accumulation, to set at least one of the logic levels. A first electrode is coupled to bias the BTBT device with a first bias voltage that is higher than the first threshold voltage. The first bias voltage is controlled such that the BTBT device is in accumulation during a write operation. The injected amount of charge on the floating gate is determined by the first bias voltage.