The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 19, 2010
Filed:
Jul. 01, 2005
Charles M. Branch, Dallas, TX (US);
Steven C. Bartling, Plano, TX (US);
Marc Edward Royer, Garland, TX (US);
Cory Dean Stewart, Richardson, TX (US);
Charles M. Branch, Dallas, TX (US);
Steven C. Bartling, Plano, TX (US);
Marc Edward Royer, Garland, TX (US);
Cory Dean Stewart, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.