The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2010

Filed:

Jun. 17, 2008
Applicants:

Junji Toyomura, Nagasaki, JP;

Yukitoshi Yamashita, Nagasaki, JP;

Shogo Nakamura, Nagasaki, JP;

Norifumi Kanagawa, Nagasaki, JP;

Yasuhide Shimizu, Nagasaki, JP;

Koichi Ono, Kanagawa, JP;

Inventors:

Junji Toyomura, Nagasaki, JP;

Yukitoshi Yamashita, Nagasaki, JP;

Shogo Nakamura, Nagasaki, JP;

Norifumi Kanagawa, Nagasaki, JP;

Yasuhide Shimizu, Nagasaki, JP;

Koichi Ono, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

A flash A/D converter includes a reference voltage generator for generating a plurality of reference voltages, a first group of amplifiers having a plurality of amplifiers each of which amplifies a difference voltage between each reference voltage generated by the reference voltage generator and a voltage of an input signal, and a second group of amplifiers having a plurality of amplifiers. Each amplifier of the first group of amplifiers is a differential amplifier having a different pair formed of a plurality of sets of cascade-connected transistors, and has a first switch for short-circuiting respective cascade connection portions of the plurality of transistors configuring the differential pair. Each amplifier of the second group of amplifiers is a differential amplifier having a differential pair formed of at least two transistors and has a second switch for short-circuiting a portion between input units of the differential pair. The first switch and the second switch are controlled to open and close by a control clock of a predetermined period.


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