The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 19, 2010
Filed:
Dec. 14, 2007
Hiroki Yamashita, Hachioji, JP;
Fumio Yuuki, Fujimino, JP;
Ryo Nemoto, Kokubunji, JP;
Hisaaki Kanai, Yokohama, JP;
Keiichi Yamamoto, Yamato, JP;
Hiroki Yamashita, Hachioji, JP;
Fumio Yuuki, Fujimino, JP;
Ryo Nemoto, Kokubunji, JP;
Hisaaki Kanai, Yokohama, JP;
Keiichi Yamamoto, Yamato, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A level conversion circuit capable of realizing low-power/high-speed operation and suppression of variations in input/output characteristics due to variations in source voltage and temperature and device variation. The level conversion circuit comprises: a source follower circuit including a first transistor to input an AC signal of CML level thereto and a second transistor to input a control voltage thereto; and a control-voltage generating circuit to generate the control voltage to be inputted to the second transistor. The control-voltage generating circuit comprises: a replica source follower circuit which is a replica of the source follower circuit including a third transistor to input a central voltage of CML level thereto and a fourth transistor to input the control voltage thereto; and a comparator which controls the control voltage, thereby equalizing an output voltage of the replica source follower and a threshold voltage of a CMOS circuit.