The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 19, 2010
Filed:
Mar. 08, 2006
Tsukasa Shiraishi, Osaka, JP;
Yukihiro Ishimaru, Osaka, JP;
Seiji Karashima, Osaka, JP;
Seiichi Natkatani, Osaka, JP;
Hiroki Yabe, Osaka, JP;
Tsukasa Shiraishi, Osaka, JP;
Yukihiro Ishimaru, Osaka, JP;
Seiji Karashima, Osaka, JP;
Seiichi Natkatani, Osaka, JP;
Hiroki Yabe, Osaka, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A highly reliable, high-productivity package equipped with a semiconductor chip, and a method for producing the same. In a package () comprising a semiconductor chip () and a mounting substrate (), a plurality of electrode terminals () are formed on the surface () of the semiconductor chip () opposing the mounting substrate side, connection terminals () respectively corresponding to the plurality of electrode terminals (), are formed on the mounting substrate (), the connection terminals () on the mounting substrate () and the electrode terminals () are electrically connected collectively by solder bumps () formed in self-assembly, an electrode pattern () not connected with the electrode terminals () and the connection terminals () is formed on the chip surface () or the surface () of the mounting substrate () corresponding to the chip surface (), and solder () is accumulated on the electrode pattern ().